PCI - FPGA - Core


The PCI bus is an integral part of many systems used to connect various components so that they can communicate. The PCI FPGA core contains an interface to the PCI bus and offers the user an easy-to-use 31 bit address and data bus interface for data exchange.

The interface was designed in consideration of the PCI specifications 2.2 and 2.3. The FPGA core can be parametrised and adjusted to the corresponding application by means of a set of parameters. The core can be implemented in FPGA by different manufacturers.

PCI Evaluation Boards based on the APA and A3P module family by ACTELTM are available for the development of individual applications.

APA PCI - Evaluation - Board

PCI Evaluation Board on APA basis
PCI Evaluation Board on APA basis

The APA board is equipped with a 5 V 31 bit PCI connector and can be loaded with an APA075 or a pin-compatible bigger module. It has 1 Mbyte SRAM and connectors for expansions.

A3P PCI - Evaluation - Board

PCI Evaluation Board on A3P basis
PCI Evaluation Board on A3P basis

The A3P Board is equipped with a universal connector for 3.3 V and 5 V 32 bit PCI slots. It can be loaded with A3P250, A3P400, A3P1000 or A3PE600. All free PIN are placed on connectors. With this board, it is possible to set IO voltage (3.3 V / 1.5 V or user) for a “bank”.

Features of the PCI-FPGA-Core

  • 32 bit interface
  • 33 Mhz clock rate (66 Mhz optional)
  • Can be configured as PCI Target or Master / Target
  • 0 waitstate Burst Transfer
  • User interface with 32 bit address and data bus
  • Interrupt support
  • 3 configurable memory areas (BAR 0 - 2)
  • Expansion ROM Register
  • Configurable multi-channel DMA interface (only for Master / Target)


Struktur des PCI-FPGA-Core
Struktur des PCI-FPGA-Core
  • Upgrade of existing ISA systems to PCI bus
  • Connection of customer-specific interfaces to the PCI bus
  • Integration of the PCI bus core into your application design

Downloads (in German language)

Prospekt PCI-FPGA-Core

14_PCI-FPGA-Core_1.pdf [657,3 kB]

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